Real signals don't jerk.
Which step in Figure 1 best approximates the digital signals you work with every day? The piecewise-linear step starts with a jerk, mindlessly follows a perfectly uniform ramp, and smacks hard into its upper limit. Real signals don't do that. The smooth-looking curve is a Gaussian step. It is the time integral of a Gaussian bell-shaped curve. The Gaussian step has a smooth precursor, a smooth tail, and a fast, monotonic rise in the middle. It looks more like a real digital signal, and for a good reason.
In the field of linear-system analysis, the Central Limit Theorem states that the step response of any system whose performance is limited by a large number of similar bandlimiting effects tends to become Gaussian as the number of effects approaches infinity. That theorem applies to digital devices because a typical digital driver comprises many performance-limiting stages cascaded in series, all having similar bandwidths.
An I/O driver uses multiple stages to quickly convert nanoamps of current from within your silicon into milliamps of current on the PCB (printed-circuit board). A single-stage FET amplifier cannot do that job. If you make a single-stage FET gate big enough to switch PCB-level currents, there is insufficient current available at the silicon level to quickly charge that gate. A better approach breaks down the circuit into a series of multiple stages cascaded in series. Each stage is exponentially larger than the one before it. Gate-design experts spend a lot of time choosing the number of stages within each driver and carefully crafting each stage to achieve maximum performance.
That's where the Central Limit Theorem comes into play. Imagine that you are designing an I/O driver with 10 stages. At dc, the circuit works perfectly. As you go up in frequency, various parasitic effects come into play, limiting the bandwidth. Each stage suffers perhaps 20 parasitic effects, making 200 total effects you must manage to complete the design. The system behaves like a cascade of 200 tiny lowpass-filter elements connected in series. The poorest-performing elements limit the bandwidth of the whole system regardless of how well the other elements work. If you wish to raise the overall performance, you should attack the worst parts first.
Experienced IC designers successively identify the lowest-hanging effects and improve them one at a time until they have pushed every part of the system up to a uniform performance ceiling beyond which it becomes increasingly difficult to post significant gains. At that point, they stop fiddling and immediately put their product into production. This process creates a system comprising many performance-limiting stages cascaded in series, all having similar bandwidths. The Central Limit Theorem says that such systems always produce a Gaussian-shaped step response. Ergo, according to this reasoning, digital drivers should always produce Gaussian-looking signals.
Figure 1 shows that the maximum time-domain deviation
between a Gaussian step and a piecewise-linear step amounts to only 5%
(Figure 1). That amount doesn't sound like much, but those sharp corners
in the piecewise-linear curve can induce frequency-domain deviations as
large as 20 dB, a significant source of error, and a topic I will take
up in my next article, "Shaping Edges".