Article

Spread Your Returns

by Dr. Howard Johnson. First printed in EDN magazine, March 31, 2005

The other day, I touched off a rather heated discussion about ground bounce. The discussion followed my remarks that the simplistic model in Figure 1, although useful for introducing the concept of ground bounce to untutored designers, contains a fundamental flaw.

The diagram shows two totem-pole drivers connected through BGA balls to pc-board power and ground planes. In this example, assume these drivers perfectly perform their function. At time zero, close Switch A. The diagram suggests that I/O current traversing Switch A causes a voltage glitch on the chip substrate as it flows through the finite inductance, L_GND, representing the matrix of ground balls underneath your BGA package. According to the diagram, this voltage glitch should be measurable at location D, assuming Switch C remains stuck low for the duration of this experiment.

The diagram is qualitatively good at explaining why switching events on one pin cause noise on another but quantitatively poor at predicting the noise amplitude. To see why, you must abandon the concept of inductance as a property of an individual wire or conductive pathway, and begin to perceive inductance as a property of the space between conductors.

In any high-frequency inductive problem, the relevant magnetic field resides in the space between conductors, not in the conductors themselves. This field, not the conductors, causes all inductive effects.

In contrast, a tightly wrapped inductive coil concentrates its magnetic field in the space immediately surrounding the coil. If the coil is small compared with the remainder of the circuit, it is logical (and correct) to think of the inductance as residing inside the body of that inductive component.

Digital designers rarely employ coils. Their inductances spring from the magnetic fields existing in the spaces between signal and return pathways—in this case, between the signal and return balls underneath a BGA package.

Figure 2 redraws the circuit, showing the chip package on top, above the balls and vias. The vias associated with signal balls at D, F, and B each penetrate the ground plane. When Switch A closes, current traverses the path that appears in red. This action fills the entire space between Via B and the ground via with an intense magnetic field. Figure 2 partitions that field into three sections: L₁, L₂, and L₃. Faraday's law says that the crosstalk measured at D varies in proportion to the total magnetic flux, L₁, lying between Via D and the nearest return-current position. Crosstalk at F varies with the sum of fields L₁and L₂ and thus exceeds the crosstalk at D.

Here lies the flaw in Figure 1: By ascribing inductance to the ground pathway only, Figure 1 ignores the impact of signal positioning on observed crosstalk. In a real problem, ground bounce always varies with your proximity to a good return connection. The signals closest to a good return suffer the least ground bounce or "power bounce."

Put this knowledge to work on your next chip architecture. Evenly distribute your many return connections among the signal pins on your package rather than group together all returns in the core region. Spreading your returns substantially reduces crosstalk.