I don't know if this falls into your areas of expertise, though your excellent articles and book lead me to believe you might be able to help!
My question has to do with "jitter". In many serial digital systems "jitter" is specified. The spec is usually in absolute time. For example, SMPTE specifies the jitter on the parallel clock of an SDI serializer as 370 picoseconds peak to peak for a clock frequency of 27 MHz. [ED -- The bus width of this interface is 10 bits, and the serializer output rate is 270 MHz]. Compared to the serial output rate, this jitter specification amounts to 0.1 UI (unit interval) of jitter. The jitter is specified for offset frequencies between 10 Hz and 1/10 the serial clock rate. I intend to make the 27 MHz clock using a PLL, starting from the horizontal sync frequency already available for baseband video elsewhere on my card. I have obtained a plot of the phase noise in dBc vs frequency for my horizontal sync oscillator.
Can I calculate what the jitter will be from this phase noise plot? How would I do that?
My thought is to determine the jitter floor of the VCXO from the phase noise plot to determine if the oscillator can meet the design requirements and how much I can allow to be transferred from the PLL's reference (Hsync) within the loop bandwidth, for internal error budget, etc.
There was a recent  article in EDN magazine on "Clock-source Jitter", but the math didn't look correct, there were typos, and I hesitate to use a "rote" type method.
Any help or light you can shed on this problem would be appreciated.
Thanks for your interest in High-Speed Digital Design.
I've always wanted to know how to do the same calculation, so I recently researched the math and came up with an answer for you.
Here's what you need to know. For small amounts of jitter (like 0.1 UI or less), we can use what is called the "narrowband phase modulation" assumption to perform our analysis. What this says is that we can model a clock system as if it were receiving a sinusoidal clock at frequency F, to which we have added a small amount of noise, also at frequency F.
The noise has TWO important properties.
First, the noise is assumed to be in quadrature (90 degrees out-of-phase) to the main clock sinusoid. Second, the noise is amplitude modulated. If you get out a piece of paper and draw a phasor diagram you will see that the addition of small amounts of quadrature noise to a sinusoid merely accomplishes a little bit of phase modulation. In other words, we can model any sinusoidal signal with small amounts of phase modulation (which is what you have) as a combination of one main sinusoid plus a second amplitude-modulated carrier at the same frequency, but in quadrature with the first signal.
What this all means is that when you look at a spectral-power-density plot of a phase-jittery clock, what you see is one big whopping peak near the fundamental frequency of the clock, plus a lower-level spreading of power around the peak. The spreading represents the power present in the modulating signal. Now, the PLL inside your serializer circuit has a certain tracking bandwidth that will filter out all the phase noise within a certain bandwidth B of the main fundamental peak. That part of the noise is of no concern.
The only phase noise that will frustrate your serializer's PLL is the phase noise that lies further away from the fundamental than B.
In your case, you have told me that the tracking bandwidth of the relevant circuit is 10 Hz, meaning that all the noise further away than 10 Hz from the main peak will add to your jitter.
To find the total power in the modulating signal, you will have to integrate (by hand, with a calculator) the power in the spectral noise surrounding the main fundamental. If your spectrum analyzer displays units of dBV per square-root-of- Hertz, you first take a set of samples of the noise level on a dense grid of frequencies. Next convert each reading from dBV to absolute volts per square- root-of-Hertz. Then square these readings to convert to units of power/Hz (don't worry about dividing by 50ohms because that part of the calculation will be cancelled out in a minute, as you will see). Then multiply each reading (in power/Hz) times the number of Hertz between readings, and add up the results (in units of power). That's how you perform the integration.
To find the total power in the main signal, you use the same integration method, but this time integrating the power over the big fundamental peak.
NOTE: Be careful about the units used on your spectrum analyzer. With some models you must integrate both positive and negative frequencies to find the total power (effectively doubling the power measured on only one side), while on others the factor of two is already incorporated in the display and you merely need to integrate over all positive frequencies. As long as you integrate both the noise and the main peak the same exact way, you can't get into trouble. On the other hand, if you use the spectrum analyzer to integrate the noise power, but use a scope to estimate the fundamental power, then you need to consider the factor-of-two problem, plus consideration of the relation between the fundamental amplitude and the square-wave amplitude of your clock.
The ratio of the noise power to the power in the fundamental equals the variance (standard deviation squared) of the phase modulation in units of radians squared. Take the square root of this ratio to find the standard deviation of the phase modulation in units of radians. This is the RMS value of the noise signal. The last step is to translate this standard deviation into a peak-to- peak value.
To do that we will need to make an assumption about the statistics of the noise. Assuming the noise is Gaussian (and not the result of some deterministic, predictable phase wander), one normally figures that if the BER of the system is specified at, say, 1E-12, then it's OK to violate the phase jitter spec one time in 1E+12. In numerical terms, what I'm saying is that it's probably OK if the phase jitter occasionally exceeds +/- 0.05 UI (that's 0.1 UI peak-to-peak) as long as it doesn't do so more often than one time in 1E+12. The spread between the 1E-12 probability tails on a Gaussian distribution is about 14.3 standard deviations. Therefore if you want the peak-to-peak deviation (at 1E-12 BER) to equal 0.1 UI, you require a standard deviation of less than 0.1/14.3 UI, or when translated into radians, a standard deviation of less than (0.1*2*3.1415926...)/14.3. For different BER levels you have to adjust the factor of 14.3.
Regarding my calculation of the number 14.3, the sum of the cumulative probability of Gaussian noise being greater than 14.3/2 standard deviations, plus the cumulative probability of the noise being less than -14.3/2 standard deviations, adds up to 1E-12.
Dr. Howard Johnson